Nvidia can design a faster processor. SK hynix can stack more memory. Neither one becomes an AI chip until somebody joins the two together, and for many of the industry's top chips that somebody is TSMC.
The joining step is called CoWoS. It rarely makes headlines, but it decides how many finished AI chips exist. And the numbers people quote about it are shakier than they look.
What is CoWoS packaging?
CoWoS stands for Chip on Wafer on Substrate. It's TSMC's method for placing an AI processor and its memory side by side on one thin slab of silicon.
That slab is called an interposer. It works like a street grid between the processor and its memory. It carries thousands of tiny wires so data can move between them quickly. The finished stack then sits on a base board, the substrate, that connects to the rest of the server.
TSMC describes CoWoS as 2.5D packaging that integrates processors and high-bandwidth memory stacks. It isn't new. TSMC says the platform has been in volume production since 2012. What changed is demand. Each Nvidia Rubin processor carries eight memory stacks. Every one of them connects through the interposer. Our coverage of the HBM4 memory squeeze explains why that memory is scarce too.
What are CoWoS-S, CoWoS-R and CoWoS-L?
They are three versions of the same idea. The difference is what the interposer is made of and how large it can grow.
| Version | Interposer | What TSMC says about it |
|---|---|---|
| CoWoS-S | Solid silicon | Up to 3.3 times the size of a standard chip exposure, about 2,700 square millimeters |
| CoWoS-R | Polymer and copper wiring layers | In volume production since 2023 |
| CoWoS-L | Wiring layers with small silicon bridges embedded | First 3.5-times version in volume since 2024; TSMC keeps making it larger |
The size limit matters. A single chip can only be printed so large in one exposure. AI chips now pack more processor area and more memory than one exposure allows, so the interposer has to grow. CoWoS-L is TSMC's route to bigger packages. Its page says the version keeps scaling the interposer "to integrate more silicon and memory."
Why is CoWoS a bottleneck for AI chips?
Because many top AI chips need it, and TSMC can package only so many wafers a month. A processor without packaging is a part, not a product.
TrendForce relayed Taiwan press reports in December 2025. They said both CoWoS-L and CoWoS-S were fully booked, with AI orders from Nvidia, Google, Amazon and MediaTek. That's the shape of the problem. Several of the biggest chip buyers are waiting on the same packaging lines.
The interposer itself is now a supply question too. On October 8, GlobalFoundries announced a $2 billion, multi-year deal to make silicon interposers for TSMC's CoWoS at its plant in Malta, New York. DatacenterDynamics reported that volume production is expected to start ramping in the first half of 2028. We covered what that timing means for 2027 buyers in our piece on the GlobalFoundries deal.
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How much CoWoS capacity does TSMC have?
Nobody outside TSMC can say exactly. The figures in most articles are estimates from Taiwan's press, repeated until they look like facts.
Here is where the most quoted numbers come from:
| Figure | Reported by | Original source named |
|---|---|---|
| About 130,000 wafers a month by end-2026, doubling to 260,000 by end-2028 | TrendForce, September 14, 2026 | Wccftech, citing Economic Daily News |
| 120,000 to 140,000 wafers a month in 2026; demand gap narrowing from about 20% to about 10% | TrendForce, June 15, 2026 | Economic Daily News, citing institutional investors |
Three outlets, one origin. That doesn't make the numbers wrong. Economic Daily News covers Taiwan's chip industry closely. It does mean the figures are one newspaper's reporting, not TSMC disclosures. TSMC's own CoWoS page describes the technology and gives no monthly capacity.
What does a wafer a month mean?
A CoWoS wafer is a round slab of silicon 300 millimeters across, the industry standard size. Its area is about 70,700 square millimeters. A CoWoS-S interposer can be about 2,700 square millimeters. Divide one by the other and a wafer holds at most about 26 of the largest interposers, before losses at the round edges. That is our rough arithmetic, not a TSMC figure, but it shows why bigger AI chips eat capacity fast. As interposers grow, each wafer yields fewer finished packages.
Isn't the bottleneck just making the chips?
No. Making the processor and packaging it are separate steps with separate capacity, and either one can hold up a finished AI chip.
A headline about a new chip factory says little about packaging capacity. A processor can be finished on time and still wait for a CoWoS slot. Testing is another step again, as our piece on how AI chips are tested explains.
The risk in a borrowed number
The risk is planning around a number nobody has confirmed. If the 260,000-wafer target for 2028 slips, chip makers and their customers absorb the delay. The public would likely hear about it through the same press channel that reported the target.
To be fair, TrendForce says CoWoS has been in short supply since 2023. It also cites a TSMC plan to expand capacity by over 60% by 2027. Outside firms like GlobalFoundries are joining in. A long shortage is also one the industry is spending to fix.
What date settles the CoWoS question?
Watch GlobalFoundries' Malta plant. Its interposer ramp is the clearest dated milestone in public, and it's expected in the first half of 2028.
Next milestone
GlobalFoundries' Malta, New York interposer line: volume production expected to start ramping in the first half of 2028.
When you read that an AI chip is "sold out," CoWoS is often part of the reason. The processor gets the press release. The packaging line decides how many ship.
Sources
- TSMC: CoWoS (3DFabric technology page)
- TrendForce: TSMC's CoWoS-L/S reportedly fully booked (December 8, 2025)
- TrendForce: CoWoS supply-demand gap reportedly narrowing (June 15, 2026)
- TrendForce: CoWoS capacity reportedly to double by 2028 (September 14, 2026)
- TrendForce press release: advanced packaging and CoWoS supply (April 30, 2026)
- DatacenterDynamics: GlobalFoundries signs $2bn, five-year deal with TSMC (October 8, 2026)
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