What is the part between an AI chip and its memory?

An AI chip does not work alone. It sits beside stacks of memory, and a thin slab of silicon called an interposer connects them.

TSMC's name for the packaging that does this is CoWoS, short for Chip-on-Wafer-on-Substrate. Think of the interposer as the street grid between a processor and its memory. The chip and the memory can both be perfect, and the system still won't run without the grid between them.

At TSMC's third-quarter call this month, CEO C.C. Wei said CoWoS "remained customers' top choice for integrated circuit assembly," as Focus Taiwan reported it. Most buyers of AI servers never see this step. It can still hold up a delivery.

What did GlobalFoundries and TSMC actually agree to?

GlobalFoundries will make silicon interposers for TSMC's CoWoS packaging at its Malta, New York plant. The initial term is five years.

Volume production is expected to ramp in the first half of 2028. Embedded Computing Design, which reported the announcement on October 13, says the agreement also covers embedded deep trench capacitor components and sets a framework for adding capacity as customer demand grows. Press coverage puts the value at about $2 billion. The companies describe Malta as the first U.S.-based source of these interposers.

GlobalFoundries senior vice president Ed Kaste said "advanced packaging is becoming increasingly critical" and called the deal "a secure, scalable source of essential advanced-packaging elements." What the companies left out matters as much as what they said.

Item What was reported What was not disclosed
Value About $2 billion How much is plant spending and how much is prepaid wafers
Term Five years initial, with room to expand How much capacity the expansion adds
Volume timing Ramp in the first half of 2028 Actual volumes and TSMC's share of Malta's output
Customer Not named Who ends up using these interposers
Scope Interposers for TSMC's CoWoS Whether every CoWoS variant is covered

Read the table from a buyer's side. Every blank in the right-hand column is a question you could put to a vendor, and probably can't get answered yet. The customer isn't named, so you can't tell whether your vendor's chips are in line for this supply. Volumes aren't given, so you can't tell how much of the 2028 ramp is already spoken for. That is normal for a deal announced this early. It also means the headline number tells you very little about your own order.

Does this create a fully U.S.-made AI chip package?

Not by itself. Coverage of the deal says final assembly, testing and the memory involve separate steps and separate suppliers.

Embedded Computing Design describes only the interposer. It does not mention U.S. assembly. In September, TrendForce passed along a Taiwanese press report, which TSMC has not confirmed, that CoWoS capacity could double from about 130,000 wafers a month at the end of 2026 to about 260,000 by the end of 2028. The report centers that build on Taiwan and TSMC's Arizona campus.