How do you know a tiny chip works before you build around it?
You test it early. Chips are checked while still on the wafer, before packaging, because a bad chip costs more the later someone finds it.
A wafer is a thin disc of silicon that holds many finished chips. You can't tell by looking which ones work. Picture one wafer under the probe: a chip fails and gets marked, so nobody packages it. That small act is the whole point of the step.
FormFactor, which makes the needle-covered cards used for this job, says testing at the wafer level lets engineers "catch defects early, before investing in expensive packaging steps." That is a vendor's view of its own market. It is also plain logic.
Why are AI chips harder to test than ordinary chips?
AI chips use stacked, advanced packaging, which FormFactor says brings risks that can't be spotted after packaging and pushes the limits of wafer testing.
Advanced packaging joins several chips into one unit, and Nexairi has covered the packaging bottleneck. Packaging is where the money goes. A defect caught before that step saves the spend.
FormFactor puts the problem this way: stacked designs "introduce new reliability risks and yield challenges that can't be spotted after packaging." The company also says AI chips are "so complex, they're really pushing the limits of what traditional wafer testing can handle." Both are claims from a company that sells test equipment.
What does a wafer prober do?
A wafer prober holds the wafer and moves it so a probe card's needles can touch each chip. It is one link in the chain.
The probe card is covered in tiny needles that touch each chip's contacts. A separate tester sends signals through those needles and reads what comes back. Three machines, three jobs.
Tokyo Electron describes its Prexa line as "a fully automated and most advanced wafer prober series" and says 3D stacking needs "a wafer testing process with reliable KGD performance." KGD means known good die: a chip confirmed to work before anyone builds around it.
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Why does a chip that carries light need a different test?
Light needs a fiber lined up with the chip, to a fraction of a micron, on top of the usual electrical contact.
Most chips move signals as electricity. Some newer designs also move signals as light. These photonic integrated circuits, or PICs, need two kinds of connection at once. Electrical testing means touching a contact. Light needs a fiber aimed at the right spot.
A 2026 paper in the journal Chips, by researchers at probe card maker Technoprobe and Politecnico di Milano, says photonic devices bring "the critical requirement to establish a stable and repeatable optical interface" alongside the usual electrical contact. It adds that light coupling "degrades sharply with even sub-micron" misalignment. Sub-micron means less than a millionth of a meter.
The authors work for a company that sells into this market, so read the paper as an industry view. Its framing is still useful. It says the wafer-level optical test can decide whether a photonic package is sorted as known good "before expensive assembly, optical attach and package-level integration."
Tokyo Electron makes a similar point. In the transcript of its October 30 presentation, the speaker says that for silicon photonics, "wafer-level integrated tests of photonics and electronics are essential."
What did Tokyo Electron actually say?
It made three statements about probers and photonic testing. They are forecasts and company claims, and they carry different weight.
| Statement | Where | What it is |
|---|---|---|
| "Record-high shipments expected (approx. +60% YoY)" | Slide 15 | A forecast for probers overall. It does not break out photonic testing. |
| "Volume production ramping for integrated optical/electrical testing of PICs" | Slide 15 | A company statement. No customer, volume or test result is named. |
| Won a "POR" for a silicon photonics prober and expects "contribution to our future sales" | Speaker's notes | A company expectation of later sales. It gives no date or amount. |
The speaker ties the first line to "a clear No.1 share in advanced logic," which is Tokyo Electron's own claim. Nothing in the document says how much of the growth comes from photonic chips.
The second and third lines sit a little apart. The slide says volume production is ramping. The speaker's notes say the company has won POR and expects sales to follow. They may describe different things. The document doesn't say.
Two readings of one slide
The supported reading is narrow. Tokyo Electron expects to ship many more probers and says a photonic test product is moving into production.
Everything past that is open. Growth could come from new chip technology or from the company winning share. It could be both. The slide doesn't show a shortage of testing capacity, and this article doesn't claim one. Separate reporting of photonic prober sales would help settle it.
What would show the test step is working?
A forecast is a starting point. It becomes a record when shipments arrive, a named factory uses the tool and test results are public.
Four pieces of evidence would move this from plan to proof:
- Prober shipments reported against the 60% forecast, so the gap between expected and delivered is visible
- A named production line that uses the photonic test tool, since a customer's use is stronger than a vendor's claim
- Test results, such as how many photonic chips pass, which would show whether the test step is a bottleneck
- Photonic prober sales broken out from the rest, so the growth can be traced to its source
What This Means for You
The upside: a new kind of chip needs a matching test before it can ship in volume, and a company has said that test is moving toward production.
The risk: a forecast isn't a result. Nothing public yet shows who is buying the photonic test tool or how well it works.
The next question: when you read about a new AI chip, ask how it is tested and whether that test has run in a real factory. Light-based parts like PsiQuantum's optical switch face the same question.
The next check is Tokyo Electron's next quarterly update. Until a customer names the tool or someone publishes test results, the photonic test step is a claim, not a record.
Sources
- Tokyo Electron: Investor presentation and transcript, October 30, 2026 (slide 15)
- Tokyo Electron: Prexa series wafer prober
- FormFactor: The future of wafer-level testing in AI-driven chip design (August 7, 2025)
- Bejani et al., Chips 2026, 5(3), 21: A Smart, Sensor-Augmented Probe Card for Wafer-Level Photonic Testing of Co-Packaged Optics Devices (August 2, 2026)
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Jim Smart is the founder and editor in chief of Nexairi. A Business Intelligence Developer with experience building data systems for Verizon, U.S. Army operations, and enterprise finance teams, Jim spent years turning complex data into decisions that executives could act on — dashboards, forecasting models, and automation pipelines across telecom and government contracting. He founded Nexairi to apply that same clarity to AI: making emerging technology understandable and actionable for the operators, accountants, and business owners who need it most. Jim holds GenAI certifications from the University of South Florida Bellini College of AI and completed Springboard's Data Science Career Track.
